As is known in the art, it is frequently required to forming anti-reflection coatings on selected areas of an optical window wafer used in wafer level packaging of optical elements. In one application, for example, wafer level packaging of Infrared (IR) bolometers, an optical window wafer (sometimes referred to as a cap wafer) has a plurality of cavities or recesses formed in a surface thereof, each recess being formed to provide a cavity (with vertically extending walls) associated with (spaced from and disposed over) a corresponding one of a plurality of IR detector (e.g., bolometers) arrays formed in a second, underlying wafer bonded to the cap wafer. In addition to the recesses, the cap wafer also includes a patterned anti-reflective coating (ARC), thin film getters, if required, and bond structures.
As is also known in the art, coating a window cap wafer with an anti-reflection coating for wafer level packaged IR bolometer detectors is currently done by coating the optical window through a shadow mask or by coating the whole surface (top surface and cavity surface) and polishing off the upper surface. A photolithographic resist lift-off method may also be used, but expensive capital equipment is required. The shadow mask adds the cost of the mask (often only good for a single use) and alignment tooling. Polishing requires precision polishing equipment and skilled operators. Both require clearing to a higher level than is typical in the optics industry. Thus, patterning an anti-reflective coating on a surface can be difficult with traditional methods, which are 1. Shadow mask (limited by alignment tolerance, edge sharpness). 2. Photolithographic lift-off (ARCs are typically too thick for easy photoresist lift-off, and require capital equipment. Lift-off is an undesirable messy process in the semiconductor industry). 3. If over topology where recessed surface is to be coated and upper surface to be removed, polish off of upper surface may be used (requires precision optical polishing equipment). All of these have problematic issues when applied to the semiconductor world, particularly with cleanliness and particle control.
The basic wafer level packaging process may be summarized as: Etch cavities in cap wafer; Deposit an ARC on the bottom of the cavity, Metalize a seal ring pattern on the top surface of the cap wafer surrounding the cavity; Deposit getter material on another portion of the top surface, if required; Apply solder to seal ring area; and to IR detector device wafer; and Saw into individual detector arrays.